1. Field of the Invention
The present invention relates to cryptographic algorithms and apparatus for implementing such cryptographic algorithms, and in particular to a method for modular multiplication using a multiplication look-ahead process and a reduction look-ahead process.
2. Description of the Related Art
Cryptography is one of the essential applications of modular arithmetic. An essential algorithm for cryptography is the known RSA algorithm. The RSA algorithm is based on a modular exponentiation that can be represented as follows:C=Mdmod(N),wherein C is an encrypted message, M is a non-encrypted message, d is the secret key and N is the modulus. Modulus N usually is generated by multiplication of two prime numbers p and q. The modular exponentiation is broken down into multiplications by means of the known square-and-multiply algorithm. To this end, the exponent d is broken down into powers of two so that the modular exponentiation may be broken down into several modular multiplications. For being able to efficiently implement the modular exponentiation in terms of computation, the modular exponentiation thus is broken down into modular multiplications, which may then be broken down into modular additions.
The document DE 3631992 C2 discloses a cryptographic process in which the modular multiplication can be accelerated using a multiplication look-ahead process and a reduction look-ahead process. The process described in DE 3631992 C2 is also referred to as ZDN method and will be explained in more detail by way of FIG. 9. After a start step 900 of the algorithm, the global variables M, C and N are initialized. The object consists in computing the following modular multiplication:Z=M*CmodN. M is the multiplier, whereas C is the multiplicand. Z is the result of the modular multiplication, whereas N is the modulus.
Then, there are various local variables initialized that need not be dealt with in more detail for the time being. Thereafter, two look-ahead processes are employed. In the multiplication look-ahead process GEN_MULT_LA, a multiplication shift value sz as well as a multiplication look-ahead parameter a are calculated (910) employing various look-ahead rules. Following this, the current contents of the Z register are subjected to a left-shift operation by sz digits (920).
Substantially parallel therewith, there is carried out a reduction look-ahead process GEN_Mod_LA (930) for calculating a reduction shift value SN and a reduction parameter b. In a step 940, the current content of the modulus register, i.e. N, is shifted by SN digits to the left or to the right, respectively, in order to produce a shifted modulus value N′. The central three-operand operation of the ZDN method takes place in a step 950. In this step, the intermediate result Z′ after step 920 is added to the multiplicand C that has been multiplied by the multiplication look-ahead parameter a, and to the shifted modulus N′ that as been multiplied by the reduction look-ahead parameter b. Depending on the current situation, the look-ahead parameters a and b may have a value of +1, 0 or −1.
A typical case is that the multiplication look-ahead parameter a is +1 and that the reduction look-ahead parameter b is −1, so that the multiplicand C is added to a shifted intermediate result Z′, and the shifted modulus N′ is subtracted therefrom. a will have a value of 0 if the multiplication look-ahead process would allow more than a preset number of individual left-shifts, i.e. if sz is greater than the maximum admissible value of sz, which is also referred to as k. In the event that a is 0 and that Z′, due to the preceding modular reduction, i.e. the preceding subtraction of the shifted modulus, still is quite small, in particular smaller than the shifted modulus N′, no reduction has to take place to that the parameter b is 0.
Steps 910 to 950 are carried out until all digits of the multiplicand have been worked off or processed, i.e. until m is 0 and also until a parameter n is 0; this parameter indicates whether the shifted modulus N′ still is greater than the original modulus N or whether, despite the fact that all digits of the multiplicand have already been worked off, still further reduction steps have to be carried out by subtraction of the modulus from Z.
Finally, it is determined whether Z is smaller than 0. If this is the case, it is necessary for achieving a final reduction that modulus N be added to Z so that the correct result Z of the modular multiplication is obtained in the end. In a step 960, the modular multiplication by way of the ZDN method is concluded.
The multiplication shift value sz as well as the multiplication parameter a that are calculated in step 910 by the multiplication look-ahead algorithm, result from the topology of the multiplier as well as by the look-ahead rules employed which are described in DE 3631992 C2.
The reduction shift value SN as well as the reduction parameter b, as described in DE 3631992 C2 as well, are determined by way of a comparison of the current contents of the Z register with a value ⅔ times N. This comparison gives the ZDN method its name (ZDN=Zwei Drittel N (=two thirds N)).
The ZDN method as illustrated in FIG. 9 returns the modular multiplication to a three-operand addition (block 950 in FIG. 9), in which the multiplication look-ahead process and, concomitantly therewith, the reduction look-ahead process, are employed for increasing computing time efficiency. Thus, an advantage in terms of computing time can be achieved in comparison with the Montgomery reduction.
In the following, the reduction look-ahead process performed in block 930 of FIG. 9 will be discussed in more detail by way of FIG. 10. Firstly, in a block 1000, a reservation is carried out for the local variables, i.e. the reduction look-ahead parameter b and the reduction shift value SN. In a block 1010, the reduction shift value SN is initialized to zero. Then, the value ZDN is calculated in a block 1020, which is equal to ⅔ of modulus N. This value determined in block 1020 is stored in a register of its own, namely the ZDN register, in the crypto coprocessor.
It is then determined in a block 1030 whether the variable n is 0 or whether the shift value SN is −k. k is a value that defines the maximum shift value preset by the hardware. In the first pass, block 1030 is answered NO such that in a block 1040, parameter n is decremented and that in a block 1060, the reduction shift value is decremented by 1 as well. In a block 1080, the variable ZDN then is allocated anew, namely with half of its value, which may easily by achieved by a right-shift of the value contained in the ZDN register. It is then determined in a block 1100 whether the absolute value of the current intermediate result is greater than the value contained in the ZDN register.
This comparison operation in block 1100 is the central operation of the reduction look-ahead process. If the question is answered YES, the iteration is terminated, and the reduction look-ahead parameter b will be allocated as shown in block 1120. If, in contrast thereto, the question to be answered in block 1100 is answered NO, the iteration jumps back in order to examine the current values of n and SN in block 1030. If block 1030 is answered YES at any time in the iteration, the sequence jumps back to a block 1140 in which the reduction parameter b is set to zero. In the three-operand operation illustrated in block 950, this has the effect that no modulus is added or subtracted, which means that the intermediate result Z was so small that no modular reduction was necessary. In a block 1160, the variable n then is allocated anew, and in a block 1180 finally the reduction shift value SN is computed which is required in a block 940 of FIG. 9 in order to perform the left-shift of the modulus so as to obtain a shifted modulus.
In blocks 1200, 1220 and 1240, the current values of n and k are finally examined with respect to further variables MAX and cur_k for examining the current allocation of the N register, in order to make sure that no register exceeding takes place. The closer details are not relevant to the present invention, but are described in detailed manner in DE 3631992 C2.
The algorithm shown in FIGS. 9 and 10 can be implemented in terms of hardware as illustrated in FIG. 7. For the three-operand operation to be carried out in block 950, there is required an arithmetic unit 700, designated AU in FIG. 7. The latter is coupled with a register C 710 for the multiplicand, a register N 720 for the modulus and a register Z 730 for the current intermediate result of the modular multiplication. FIG. 7 reveals furthermore that the result of the three-operand operation, via a feedback arrow 740, is fed back to Z register 730. FIG. 7 illustrates furthermore the mutual connection of the registers. The value ZDN computed in block 1020 of FIG. 10 has to be stored in a ZDN register 750 of its own. The ZDN comparison, i.e. the iteration loop shown in FIG. 10, furthermore is controlled in its progress by a control logic 760 for the ZDN comparison of its own.
The main work of the ZDN algorithm for computing Z:=M×C mod N thus consists in the following two operations:
1. Computing the shift values sz and si for the registers Z and N so as to fulfill the following equation:⅔N×2−si<|Z|≦ 4/3N×2−si and
2. Computing the three-operand sum:Z:=2sZZ+aC+b×2sz−siN, 
The multiplication look-ahead parameter a and the reduction look-ahead parameter b may assume values of −1, 0 and +1, as is known.
It is to be pointed out that the intermediate result Z, the multiplicand C and the modulus N are long numbers, i.e. numbers whose count of digits or bits may indeed be greater than 512, and which may also have up to more than 2048 digits.
The comparison of the current intermediate result Z with the value ZDN, which is to be carried out in block 1100, however, is not carried out for all bits of Z for reasons of computation time, but only with a number of most significant bits of Z; in this respect, a number of 32 bits has turned out to be sufficient for obtaining very high accuracy for the comparison result.
For the 32 most significant bits of ⅔ N required for this comparison, a register of its own is necessary which in FIG. 7 is indicated under reference numeral 750 and which is referred to as ZDN register.
Furthermore, a hardware comparator of its own is necessary which computes for the current value in the Z register and for the current value in the ZDN register the correct si value so that the following equation is fulfilled:⅔2−siN<|Z|≦ 4/32−siN 
Thus, what is disadvantageous in this method is on the one hand that both the additional ZDN register and the hardware comparator require extra chip area. On the other hand, the computation of ⅔ N and the computation of the auxiliary shift value si in the ZDN algorithm performed by the iteration loop shown in FIG. 10 are time-critical for the entire algorithm and may indeed be determinative for the overall execution time of the algorithm.